There is a trend in the electronics industry to reduce the size of components of electronic devices. Such a reduction in size may enable reduced cost, increased efficiency, lower energy requirements, among other benefits. Semiconductor device packages (e.g., memory, processors, light-emitting diodes (LEDs), micro-electromechanical system (MEMS) device packages, etc.) have been the subject of a variety of size reduction efforts. For example, one method of reducing the thickness of semiconductor devices and packages includes using so-called “through-silicon vias” (TSVs). In so-called “three-dimensional (3D) integration,” for example, electrical access to stacked semiconductor dice is provided through the TSVs. Semiconductor wafers including TSVs are often thinned to form semiconductor dice that may be stacked to form semiconductor device packages of a relatively low height. Such thinning renders the semiconductor wafer fragile and difficult to handle during subsequent processing. Accordingly, the semiconductor wafer may be temporarily bonded to a carrier substrate to provide mechanical stability and strength during thinning and subsequent processing.
FIGS. 1A through 1C illustrate a conventional method of processing a semiconductor device wafer 10. With reference to FIG. 1A, a device region 12 is defined by a portion of the semiconductor device wafer 10 proximate a front surface 14 thereof, which may also be characterized as an “active surface” on which integrated circuitry is formed. The device region 12 includes features of a semiconductor device to be formed from the semiconductor device wafer 10, such as through-silicon vias (TSVs) 18, extending from the front surface 14 into and at least partially through the device region 12. The semiconductor device wafer 10 is bonded to a relatively rigid carrier substrate 20 with a temporary adhesive 30 including a thermoplastic polymer material and a solvent, which is subjected to heat to remove at least a portion of the solvent. A top surface 22 of the carrier substrate 20 includes an edge region 28 proximate a peripheral edge 26 of the carrier substrate 20 that does not directly underlie the device region 12.
After bonding the semiconductor device wafer 10 to the carrier substrate 20, the semiconductor device wafer 10 may be subjected to further processing, which is often referred to in the art as “back side processing.” For example, material may be removed from a back surface 16 of the semiconductor device wafer 10 by mechanical grinding and/or polishing, (e.g., coarse mechanical grinding, fine mechanical grinding, chemical-mechanical polishing (CMP), or any combination thereof) to leave a thinned semiconductor device wafer 11 (referred to below as “thinned wafer 11” for simplicity), as shown in FIG. 1B. After thinning, other processes may be performed on the back surface 16 of the thinned wafer 11, such as material removal, cleaning, and material formation.
Referring to FIG. 1C, processes that involve application of heat to the thinned wafer 11 and, consequently, to the temporary adhesive 30, may cause the temporary adhesive 30 to soften and flow to contaminate one or both of the back surface 16 of the thinned wafer 11 and a bottom surface 24 of the carrier substrate 20. Such contamination may cause difficulties and errors in subsequent processing of the thinned wafer 11. In some cases, the entire thinned wafer 11 or portions thereof may be rendered useless due to the contamination of the back surface 16 and/or the bottom surface 24 with the temporary adhesive 30. After back side processing is complete, the thinned wafer 11 of FIG. 1B or 1C is debonded from the carrier substrate 20 by applying a shear stress and heat to the temporary adhesive 30.
FIGS. 2A through 2C illustrate another method of processing a thinned semiconductor device wafer 11. After the thinned wafer 11 is formed and a bond is established between the thinned wafer 11 and the carrier substrate 20 with the temporary adhesive 30, as described above with reference to FIGS. 1A and 1B, the temporary adhesive 30 is removed from the edge region 28 of the carrier substrate 20, as shown in FIG. 2A, by a so-called “edge cleaning” process. The exposed temporary adhesive 30 is removed by applying a suitable solvent. The solvent may be applied in a manner such that a portion of the temporary adhesive 30 underlying a peripheral edge 40 of the thinned wafer 11 is removed, in addition to the portion over the edge region 28.
Referring to FIG. 2B, the temporary adhesive 30 may be subjected to an elevated temperature (e.g., between about 150° C. and about 300° C., such as between about 180° C. and about 220° C.) to soften and flow the temporary adhesive 30 to support the peripheral edge 40 and to remove solvent introduced and absorbed by the temporary adhesive 30 during the edge cleaning. As a result of the heating, a portion of the temporary adhesive 30 may flow onto the edge region 28. As the temporary adhesive 30 softens under the elevated temperature, an average bond line thickness TBL of the temporary adhesive 30 may be reduced, at least proximate the peripheral edge 40, due to the flowing of the temporary adhesive 30 onto the edge region 28. As shown in FIG. 2C, subsequent processing operations that involve application of heat may cause the temporary adhesive 30 to continue to flow further onto the edge region 28 of the carrier substrate 20.
The method described with reference to FIGS. 2A through 2C may reduce a risk of contamination of the back surface 16 of the thinned wafer 11 and of the bottom surface 24 of the carrier substrate 20 compared to the method described with reference to FIGS. 1A through 1C. However, there may still be some risk that contamination of one or both of the back surface 16 of the thinned wafer 11 and the bottom surface 24 of the carrier substrate 20 due to flowing temporary adhesive 30 may occur during processing operations that involve heat. In addition, non-uniformity caused by reduction of the average bond line thickness TBL proximate the peripheral edge 40 may reduce control and reliability of back side processes performed on the thinned wafer 11.
Additional issues may be introduced by performing the operations described in FIGS. 2A and 2B. For example, the cleaning and subjecting to an elevated temperature may add to the time and cost of processing the thinned wafer 11. Additionally, the temporary adhesive 30 may not flow all the way to the peripheral edge 40 of the thinned wafer 11 while being subjected to an elevated temperature after cleaning the edge region 28, which may result in chipping, lifting, or delamination of the peripheral edge 40 during subsequent processing.
In addition, if the solvent is not substantially completely removed from the temporary adhesive 30 after the cleaning of the edge region 28, then one or more voids in the temporary adhesive 30 may develop during subsequent processing, causing the bond between the thinned wafer 11 and the carrier substrate 20 to weaken or even to fail (e.g., delaminate) where the void forms.
Whether the method described above with reference to FIGS. 1A through 1C or the method described above with reference to FIGS. 2A through 2C is used, the front surface 14 of the thinned wafers 11 may include irregular, which may also be characterized as nonplanar, topography (i.e., features, such as discrete conductive elements such as pads, bumps, columns, or pillars, that extend to a significant height above the front surface 14 of the thinned wafer 11). Such nonplanar topography may aggravate the problems discussed, as the topography requires additional temporary adhesive 30 to fill a gap between the thinned wafer 11 and the carrier substrate 20. The additional temporary adhesive 30 may increase a risk that the temporary adhesive 30 will flow during back side processing, potentially causing one or more of the problems discussed above.